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rev.2.10 dec 05, 2007 page 1 of 57 rej03b0183-0210 r8c/2c group, r8c/2d group renesas mcu 1. overview 1.1 features the r8c/2c group and r8c/2d group of single-chip mcus incorporates the r8c/tiny series cpu core, employing sophisticated instructions fo r a high level of efficiency. with 1 mb yte of address space, and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus also use an anti-noise configuration to reduce emissions of electro magnetic noise and are designed to withstand emi. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. furthermore, the r8c/2d group has on-chip data flash (1 kb 2 blocks). the difference between the r8c/2c group and r8c/2d group is only the presence or absence of data flash. their peripheral functions are the same. 1.1.1 applications electronic household appliances, office equipment, audio equipment, cons umer equipment, etc. rej03b0183-0210 rev.2.10 dec 05, 2007
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 2 of 57 rej03b0183-0210 1.1.2 specifications tables 1.1 and 1.2 outlines the specifications for r8c/2c group and tables 1.3 and 1.4 outlines the specifications for r8c/2d group. table 1.1 specifications for r8c/2c group (1) item function specification cpu central processing unit r8c/tiny series core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram refer to table 1.5 product list for r8c/2c group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 i/o ports programmable i/o ports ? input-only: 2 pins ? cmos i/o ports: 71, selectable pull-up resistor ? high current drive ports: 8 clock clock generation circuits 3 circuits: xin clock oscillation circ uit (with on-chip feedback resistor), on-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator ha s a frequency adjustment function), xcin clock oscillation circuit (32 khz) ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed cl ock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? external: 5 sources, inte rnal: 23 sources, software: 4 sources ? priority levels: 7 levels watchdog timer 15 bits 1 (with prescaler), reset start selectable timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer rd 16 bits 2 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 6 pins), reset synchronous pwm mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary pwm mode (output three-phase waveforms (6 pins), triangular wave modulation), pwm3 mode (pwm output 2 pins with fixed period) timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode timer rf 16 bits 1 (with capture/compare register pin and compare register pin) input capture mode, output compare mode
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 3 of 57 rej03b0183-0210 notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d version if d ve rsion functions are to be used. 3. please contact renesas technology sales offices for the y version. table 1.2 specifications for r8c/2c group (2) item function specification serial interface uart0, uart1, uart2 clock synchronous serial i/o/uart 3 clock synchronous serial i/o with chip select (ssu) 1 (shared with i 2 c-bus) i 2 c bus (1) 1 (shared with ssu) lin module hardware lin: 1 (timer ra, uart0) a/d converter 10-bit resolution 20 channels, includes sample and hold function, with sweep mode d/a converter 8-bit resolution 2 circuits flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure endurance: 100 times ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function operating frequency/supply voltage f(xin) = 20 mhz (vcc = 3.0 to 5.5 v) f(xin) = 10 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 2.2 to 5.5 v) current consumption 12 ma (vcc = 5.0 v, f(xin) = 20 mhz) 5.5 ma (vcc = 3.0 v, f(xin) = 10 mhz) 2.1 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) 0.65 a (vcc = 3.0 v, stop mode) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (2) -20 to 105 c (y version) (3) package 80-pin lqfp package code: plqp0080kb-a (previous code: 80p6q-a)
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 4 of 57 rej03b0183-0210 table 1.3 specifications for r8c/2d group (1) item function specification cpu central processing unit r8c/tiny series core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram refer to table 1.6 product list for r8c/2d group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 i/o ports programmable i/o ports ? input-only: 2 pins ? cmos i/o ports: 71, selectable pull-up resistor ? high current drive ports: 8 clock clock generation circuits 3 circuits: xin clock oscillation circ uit (with on-chip feedback resistor), on-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator ha s a frequency adjustment function), xcin clock oscillation circuit (32 khz) ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed cl ock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? external: 5 sources, inte rnal: 23 sources, software: 4 sources ? priority levels: 7 levels watchdog timer 15 bits 1 (with prescaler), reset start selectable timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer rd 16 bits 2 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 6 pins), reset synchronous pwm mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary pwm mode (output three-phase waveforms (6 pins), triangular wave modulation), pwm3 mode (pwm output 2 pins with fixed period) timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode timer rf 16 bits 1 (with capture/compare register pin and compare register pin) input capture mode, output compare mode
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 5 of 57 rej03b0183-0210 notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d version if d ve rsion functions are to be used. 3. please contact renesas technology sales offices for the y version. table 1.4 specifications for r8c/2d group (2) item function specification serial interface uart0, uart1, uart2 clock synchronous serial i/o/uart 3 clock synchronous serial i/o with chip select (ssu) 1 (shared with i 2 c-bus) i 2 c bus (1) 1 (shared with ssu) lin module hardware lin: 1 (timer ra, uart0) a/d converter 10-bit resolution 20 channels, includes sample and hold function, with sweep mode d/a converter 8-bit resolution 2 circuits flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure enduranc e: 10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function operating frequency/supply voltage f(xin) = 20 mhz (vcc = 3.0 to 5.5 v) f(xin) = 10 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 2.2 to 5.5 v) current consumption 12 ma (vcc = 5.0 v, f(xin) = 20 mhz) 5.5 ma (vcc = 3.0 v, f(xin) = 10 mhz) 2.1 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) 0.65 a (vcc = 3.0 v, stop mode) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (2) -20 to 105 c (y version) (3) package 80-pin lqfp package code: plqp0080kb-a (previous code: 80p6q-a)
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 6 of 57 rej03b0183-0210 1.2 product list table 1.5 lists product list for r8c/2c group, figure 1. 1 shows a part number, memory size, and package of r8c/2c group, table 1.6 lists product list for r8c/2d group, and figure 1.2 shows a part number, memory size, and package of r8c/2d group. note: 1. the user rom is programmed before shipment. table 1.5 product list for r8c/2c group current of dec. 2007 part no. rom capacity ram capacity package type remarks r5f212c7snfp 48 kbytes 2.5 kbytes plqp0080kb-a n version r5f212c8snfp 64 kbytes 3 kbytes plqp0080kb-a r5f212casnfp 96 kbytes 7 kbytes plqp0080kb-a r5f212ccsnfp 128 kbytes 7.5 kbytes plqp0080kb-a r5f212c7sdfp 48 kbytes 2.5 kbytes plqp0080kb-a d version r5f212c8sdfp 64 kbytes 3 kbytes plqp0080kb-a r5f212casdfp 96 kbytes 7 kbytes plqp0080kb-a r5f212ccsdfp 128 kbytes 7.5 kbytes plqp0080kb-a r5f212c7snxxxfp 48 kbytes 2.5 kbyt es plqp0080kb-a n version factory programming product (1) r5f212c8snxxxfp 64 kbyt es 3 kbytes plqp0080kb-a r5f212casnxxxfp 96 kbytes 7 kbytes plqp0080kb-a r5f212ccsnxxxfp 128 kbytes 7.5 kbytes plqp0080kb-a r5f212c7sdxxxfp 48 kbytes 2.5 kbytes plqp0080kb-a d version r5f212c8sdxxxfp 64 kbyt es 3 kbytes plqp0080kb-a r5f212casdxxxfp 96 kbytes 7 kbytes plqp0080kb-a r5f212ccsdxxxfp 128 kbytes 7.5 kbytes plqp0080kb-a
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 7 of 57 rej03b0183-0210 figure 1.1 part number, memory size, and package of r8c/2c group part no. r 5 f 21 2c 7 s n xxx fp package type: fp: plqp0080kb-a (0.5 mm pin-pitch, 12 mm square body) rom number classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c y: operating ambient tem perature -20c to 105c (1) s: low-voltage version rom capacity 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/2c group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor note: 1. please contact renesas technology sales offices for the y version.
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 8 of 57 rej03b0183-0210 note: 1. the user rom is programmed before shipment. figure 1.2 part number, memory size, and package of r8c/2d group table 1.6 product list for r8c/2d group current of dec. 2007 part no. rom capacity ram capacity package type remarks program rom data flash r5f212d7snfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0080kb-a n version r5f212d8snfp 64 kbytes 1 kbyte 2 3 kbytes plqp0080kb-a r5f212dasnfp 96 kbytes 1 kbyte 2 7 kbytes plqp0080kb-a r5f212dcsnfp 128 kbytes 1 kbyte 2 7.5 kbytes plqp0080kb-a r5f212d7sdfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0080kb-a d version r5f212d8sdfp 64 kbytes 1 kbyte 2 3 kbytes plqp0080kb-a r5f212dasdfp 96 kbytes 1 kbyte 2 7 kbytes plqp0080kb-a r5f212dcsdfp 128 kbytes 1 kbyte 2 7.5 kbytes plqp0080kb-a r5f212d7snxxxfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0080kb-a n version factory programming product (1) r5f212d8snxxxfp 64 kbytes 1 kbyte 2 3 kbytes plqp0080kb-a r5f212dasnxxxfp 96 kbytes 1 kbyte 2 7 kbytes plqp0080kb-a R5F212DCSNXXXFP 128 kbytes 1 kbyte 2 7.5 kbytes plqp0080kb-a r5f212d7sdxxxfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0080kb-a d version r5f212d8sdxxxfp 64 kbytes 1 kbyte 2 3 kbytes plqp0080kb-a r5f212dasdxxxfp 96 kbytes 1 kbyte 2 7 kbytes plqp0080kb-a r5f212dcsdxxxfp 128 kbytes 1 kbyte 2 7.5 kbytes plqp0080kb-a part no. r 5 f 21 2d 7 s n xxx fp package type: fp: plqp0080kb-a (0.5 mm pin-pitch, 12 mm square body) rom number classification n: operating ambient te mperature -20c to 85c d: operating ambient te mperature -40c to 85c y: operating ambient tem perature -20c to 105c (1) s: low-voltage version rom capacity 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/2d group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor note: 1. please contact renesas technology sales offices for the y version.
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 9 of 57 rej03b0183-0210 1.3 block diagram figure 1.3 shows a block diagram. figure 1.3 block diagram d/a converter (8 bits 2) r8c/tiny series cpu core system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. 8 port p1 8 port p3 3 2 port p4 8 port p0 8 port p2 8 port p5 timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) timer rf (16 bits 1) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) peripheral functions watchdog timer (15 bits) a/d converter (10 bits 20 channels) lin module 8 port p6 8 port p7 8 port p8 4 port p9
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 10 of 57 rej03b0183-0210 1.4 pin assignment figure 1.4 shows pin assignment (top view). tables 1. 7 and 1.8 outlines the pin name information by pin number. figure 1.4 pin assignment (top view) 48 47 46 45 44 43 42 41 60 59 58 57 56 55 54 53 33 34 35 36 21 22 23 24 25 26 27 28 29 30 31 32 1 345678910111213141516 2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p7_0/an12 p3_5/scl/ssck p3_7/sso vcc/avcc vref p0_7/an0/da1 vss/avss p0_6/an1/da0 p0_5/an2/clk1 p6_1 p6_2 p0_3/an4 p0_2/an5 p0_0/an7 p0_1/an6 p0_4/an3 p8_2/trfo02 p2_6/trdioc1 p2_5/trdiob1 p2_4/trdioa1 p2_3/trdiod0 p2_2/trdioc0 p2_1/trdiob0 p2_0/trdioa0/trdclk p1_7/traio/int1 p1_6/clk0 p1_5/rxd0/(traio)/(int1) (2) p8_6 p8_5/trfo12 p8_3/trfo10/trfi p8_4/trfo11 p1_4/txd0 p7_5/an17 p6_6/int2/txd1 p6_7/int3/rxd1 p6_5/(clk1)/clk2 (2) p6_4/rxd2 p6_3/txd2 p3_1/trbo p3_0/trao p3_6/(int1) (2) p3_2/(int2) (2) p1_3/kl3/an11 p1_1/kl1/an9 p1_0/kl0/an8 p7_6/an18 p7_7/an19 p1_2/kl2/an10 p3_3/ssi p9_2 p5_0/trcclk p5_1/trcioa/trctrg p5_2/trciob p5_3/trcioc p5_4/trciod vcc/avcc p4_6/xin vss/avss p4_7/xout (1) p4_4/xcout p4_3/xcin p3_4/sda/scs mode reset 17 18 19 20 37 38 39 40 52 51 50 49 64 63 62 61 p8_1/trfo01 p8_0/trfo00 p6_0/treo p4_5/int0 p9_1 p9_0 p2_7/trdiod1 p8_7 p9_3 p5_7 p5_6 p5_5 p7_4/an16 p7_1/an13 p7_3/an15 p7_2/an14 r8c/2c group r8c/2d group plqp0080kb-a(80p6q-a) (top view) notes: 1. p4_7/xout are an input-only port. 2. can be assigned to the pin in parentheses by a program. 3. confirm the pin 1 position on the package by referring to the package dimensions.
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 11 of 57 rej03b0183-0210 note: 1. can be assigned to the pin in parentheses by a program. table 1.7 pin name information by pin number (1) pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter 1 p3_3 ssi 2 p3_4 scs sda 3 p5_7 4 p5_6 5 p5_5 6mode 7 xcin p4_3 8 xcout p4_4 9 reset 10 xout p4_7 11 vss/avss 12 xin p4_6 13 vcc/avcc 14 p5_4 trciod 15 p5_3 trcioc 16 p5_2 trciob 17 p5_1 trcioa/trctrg 18 p5_0 trcclk 19 p9_3 20 p9_2 21 p9_1 22 p9_0 23 p2_7 trdiod1 24 p2_6 trdioc1 25 p2_5 trdiob1 26 p2_4 trdioa1 27 p2_3 trdiod0 28 p2_2 trdioc0 29 p2_1 trdiob0 30 p2_0 trdioa0/ trdclk 31 p1_7 int1 traio 32 p1_6 clk0 33 p1_5 (int1 ) (1) (traio) (1) rxd0 34 p1_4 txd0 35 p8_7 36 p8_6 37 p8_5 trfo12 38 p8_4 trfo11 39 p8_3 trfo10/trfi 40 p8_2 trfo02 41 p8_1 trfo01 42 p8_0 trfo00 43 p6_0 treo 44 p4_5 int0 int0 45 p6_6 int2 txd1
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 12 of 57 rej03b0183-0210 note: 1. can be assigned to the pin in parentheses by a program. table 1.8 pin name information by pin number (2) pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter 46 p6_7 int3 rxd1 47 p6_5 (clk1) (1) /clk2 48 p6_4 rxd2 49 p6_3 txd2 50 p3_1 trbo 51 p3_0 trao 52 p3_6 (int1 ) (1) 53 p3_2 (int2 ) (1) 54 p1_3 ki3 an11 55 p1_2 ki2 an10 56 p1_1 ki1 an9 57 p1_0 ki0 an8 58 p7_7 an19 59 p7_6 an18 60 p7_5 an17 61 p7_4 an16 62 p7_3 an15 63 p7_2 an14 64 p7_1 an13 65 p7_0 an12 66 p0_0 an7 67 p0_1 an6 68 p0_2 an5 69 p0_3 an4 70 p0_4 an3 71 p6_2 72 p6_1 73 p0_5 clk1 an2 74 p0_6 an1/da0 75 vss/avss 76 p0_7 an0/da1 77 vref 78 vcc/avcc 79 p3_7 sso 80 p3_5 ssck scl
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 13 of 57 rej03b0183-0210 1.5 pin functions tables 1.9 and 1.10 list pin functions. i: input o: output i/o: input and output note: 1. refer to the oscillator manufacturer for oscillation characteristics. table 1.9 pin functions (1) item pin name i/o type description power supply input vcc, vss ? apply 2.2 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins (1) . to use an external clock, input it to the xin pin and leave the xout pin open. xin clock output xout o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins (1) . to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int3 iint interrupt input pins. int0 is timer rd input pin. int1 is timer ra input pin. key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o pins trdclk i external clock input pin timer re treo o divided clock output pin timer rf trfi i timer rf input pin trfo00 to trfo02, trfo10 to trfo12 o timer rf output pins serial interface clk0, clk1, clk2 i/o transfer clock i/o pins rxd0, rxd1, rxd2 i serial data input pins txd0, txd1, txd2 o serial data output pins i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin ssu ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter and d/a converter
r8c/2c group, r8c/2d group 1. overview rev.2.10 dec 05, 2007 page 14 of 57 rej03b0183-0210 i: input o: output i/o: input and output table 1.10 pin functions (2) item pin name i/o type description a/d converter an0 to an19 i analog input pins to a/d converter d/a converter da0 to da1 o d/a converter output pins i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_3 to p4_5, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_3 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. p2_0 to p2_7 also function as led drive ports. input port p4_6, p4_7 i input-only ports
r8c/2c group, r8c/2d group 2. central processing unit (cpu) rev.2.10 dec 05, 2007 page 15 of 57 rej03b0183-0210 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/2c group, r8c/2d group 2. central processing unit (cpu) rev.2.10 dec 05, 2007 page 16 of 57 rej03b0183-0210 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register th at indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0.
r8c/2c group, r8c/2d group 2. central processing unit (cpu) rev.2.10 dec 05, 2007 page 17 of 57 rej03b0183-0210 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupt are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/2c group, r8c/2d group 3. memory rev.2.10 dec 05, 2007 page 18 of 57 rej03b0183-0210 3. memory 3.1 r8c/2c group figure 3.1 is a memory map of r8c/ 2c group. the r8c/2c group has 1 mb yte of address sp ace from addresses 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0ffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocat ed higher addresses, beginning with address 00400h. for example, a 2.5-kbyte internal ram area is allocated addres ses 00400h to 00dffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks wh en interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.1 memory map of r8c/2c group undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor (reserved) (reserved) reset internal rom internal ram size address 0yyyyh 48 kbytes 64 kbytes 96 kbytes 128 kbytes ? 13fffh 1bfffh 23fffh 00dffh 00fffh 011ffh 011ffh 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch address 0xxxxh note: 1. the blank regions are reserved. do not access locations in these regions. address zzzzzh size 2.5 kbytes 3 kbytes 7 kbytes 7.5 kbytes 04000h 04000h 04000h 04000h fffffh 0ffffh 0yyyyh internal rom (program rom) expanded area internal rom (program rom) zzzzzh 0xxxxh 03000h internal ram 0wwwwh ? ? 03dffh 03fffh address 0wwwwh
r8c/2c group, r8c/2d group 3. memory rev.2.10 dec 05, 2007 page 19 of 57 rej03b0183-0210 3.2 r8c/2d group figure 3.2 is a memory map of r8c/ 2d group. the r8c/2d group has 1 mb yte of address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower ad dresses, beginning with a ddress 0ffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram area is al located higher addresses, beginning with address 00400h. for example, a 2.5-kbyte internal ram is allocated addresses 00400h to 00dffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/2d group undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor (reserved) (reserved) reset internal rom internal ram size address 0yyyyh 48 kbytes 64 kbytes 96 kbytes 128 kbytes 00dffh 00fffh 011ffh 011ffh fffffh 0ffffh 0yyyyh 00400h 002ffh 00000h internal rom (program rom) expanded area internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch address 0xxxxh address zzzzzh size 2.5 kbytes 3 kbytes 7 kbytes 7.5 kbytes internal rom (data flash) (1) notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. 0xxxxh 02400h 02bffh internal rom (program rom) zzzzzh ? 13fffh 1bfffh 23fffh 04000h 04000h 04000h 04000h 03000h internal ram 0wwwwh ? ? 03dffh 03fffh address 0wwwwh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 20 of 57 rej03b0183-0210 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.12 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1 and hardware reset. 4. power-on reset, voltage monitor 0 reset, or the lvd0on bit in the ofs register is set to 0 and hardware reset. 5. software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. 6. the csproini bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h module operation enable register mstcr 00h 0009h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (6) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h 002ah 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch high-speed on-chip oscillator control register 7 fra7 when shipping 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 00h (3) 00100000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (5) vw1c 00001000b 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h voltage monitor 0 circuit control register (2) vw0c 0000x000b (3) 0100x001b (4) 0039h 003ah 003eh 003fh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 21 of 57 rej03b0183-0210 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h timer rc interrupt control register trcic xxxxx000b 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh 004fh ssu/iic interrupt control register (2) ssuic / iicic xxxxx000b 0050h compare 1 interrupt control register cmp1ic xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh timer rf interrupt control register trfic xxxxx000b 005ch compare 0 interrupt control register cmp0ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh a/d conversion interrupt control register adic xxxxx000b 005fh capture interrupt control register capic xxxxx000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 22 of 57 rej03b0183-0210 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 00b9h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 00bah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 00bbh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 00bch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 00bdh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 00beh ss transmit data register / iic bus transmit data register (2) sstdr / icdrt ffh 00bfh ss receive data register / iic bus receive data register (2) ssrdr / icdrr ffh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 23 of 57 rej03b0183-0210 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 00c0h 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h 00d5h 00d6h 00d7h 00d8h d/a register 0 da0 00h 00d9h 00dah d/a register 1 da1 00h 00dbh 00dch d/a control register dacon 00h 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h port p5 register p5 xxh 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h 00f1h 00f2h 00f3h 00f4h port p2 drive capacity control register p2drr 00h 00f5h uart1 function select register u1sr 000000xxb 00f6h 00f7h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 xx000000b 00feh 00ffh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 24 of 57 rej03b0183-0210 table 4.5 sfr information (5) (1) note: 1. the blank regions are reserved. do not access locations in these regions address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h lin control register 2 lincr2 00h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re clock source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011111b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h 0134h 0135h 0136h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 0 1111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 25 of 57 rej03b0183-0210 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11000000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 1111 1000b 0146h timer rd counter 0 trd0 00h 0147h 00h 0148h timer rd general register a0 trdgra0 ffh 0149h ffh 014ah timer rd general register b0 trdgrb0 ffh 014bh ffh 014ch timer rd general register c0 trdgrc0 ffh 014dh ffh 014eh timer rd general register d0 trdgrd0 ffh 014fh ffh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 1111 1000b 0156h timer rd counter 1 trd1 00h 0157h 00h 0158h timer rd general register a1 trdgra1 ffh 0159h ffh 015ah timer rd general register b1 trdgrb1 ffh 015bh ffh 015ch timer rd general register c1 trdgrc1 ffh 015dh ffh 015eh timer rd general register d1 trdgrd1 ffh 015fh ffh 0160h uart2 transmit/receive mode register u2mr 00h 0161h uart2 bit rate register u2brg xxh 0162h uart2 transmit buffer register u2tb xxh 0163h xxh 0164h uart2 transmit/receive control register 0 u2c0 00001000b 0165h uart2 transmit/receive control register 1 u2c1 00000010b 0166h uart2 receive buffer register u2rb xxh 0167h xxh 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 26 of 57 rej03b0183-0210 table 4.7 sfr information (7) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 27 of 57 rej03b0183-0210 table 4.8 sfr information (8) (1) note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 01c0h 01c1h 01c2h 01c3h 01c4h 01c5h 01c6h 01c7h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h 01e1h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h 01f1h 01f2h 01f3h 01f4h 01f5h 01f6h 01f7h 01f8h 01f9h 01fah 01fbh 01fch 01fdh 01feh 01ffh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 28 of 57 rej03b0183-0210 table 4.9 sfr information (9) (1) note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020ah 020bh 020ch 020dh 020eh 020fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021ah 021bh 021ch 021dh 021eh 021fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 29 of 57 rej03b0183-0210 table 4.10 sfr information (10) (1) note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024ah 024bh 024ch 024dh 024eh 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026ah 026bh 026ch 026dh 026eh 026fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027ah 027bh 027ch 027dh 027eh 027fh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 30 of 57 rej03b0183-0210 table 4.11 sfr information (11) (1) notes: 1. the blank regions are reserved. do not access locations in these regions. 2. after input capture mode. 3. after output compare mode. address register symbol after reset 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028ah 028bh 028ch 028dh 028eh 028fh 0290h timer rf register trf 00h 0291h 00h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029ah timer rf control register 0 trfcr0 00h 029bh timer rf control register 1 trfcr1 00h 029ch capture / compare 0 register trfm0 0000h (2) 029dh ffffh (3) 029eh compare 1 register trfm1 ffh 029fh ffh 02a0h 02a1h 02a2h 02a3h 02a4h 02a5h 02a6h 02a7h 02a8h 02a9h 02aah 02abh 02ach 02adh 02aeh 02afh 02b0h 02b1h 02b2h 02b3h 02b4h 02b5h 02b6h 02b7h 02b8h 02b9h 02bah 02bbh 02bch 02bdh 02beh 02bfh
r8c/2c group, r8c/2d group 4. special function registers (sfrs) rev.2.10 dec 05, 2007 page 31 of 57 rej03b0183-0210 table 4.12 sfr information (12) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a pr ogram. use a flash programmer to write to it. address register symbol after reset 02c0h a/d register 0 ad0 xxh 02c1h xxh 02c2h a/d register 1 ad1 xxh 02c3h xxh 02c4h a/d register 2 ad2 xxh 02c5h xxh 02c6h a/d register 3 ad3 xxh 02c7h xxh 02c8h 02c9h 02cah 02cbh 02cch 02cdh 02ceh 02cfh 02d0h 02d1h 02d2h 02d3h 02d4h a/d control register 2 adcon2 00001000b 02d5h 02d6h a/d control register 0 adcon0 00000011b 02d7h a/d control register 1 adcon1 00h 02d8h 02d9h 02dah 02dbh 02dch 02ddh 02deh 02dfh 02e0h port p7 direction register pd7 00h 02e1h 02e2h port p7 register p7 xxh 02e3h 02e4h port p8 direction register pd8 00h 02e5h port p9 direction register pd9 x0h 02e6h port p8 register p8 xxh 02e7h port p9 register p9 xxh 02e8h 02e9h 02eah 02ebh 02ech 02edh 02eeh 02efh 02f0h 02f1h 02f2h 02f3h 02f4h 02f5h 02f6h 02f7h 02f8h 02f9h 02fah 02fbh 02fch pull-up control register 2 pur2 xxx00000b 02fdh 02feh 02ffh timer rf output control register trfout 00h ffffh option function select register ofs (note 2)
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 32 of 57 rej03b0183-0210 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c700mw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c the electrical characteristics of n version (topr = ?20 c to 85 c) and d version (topr = ?40 c to 85 c) are listed below. please contact renesas technology sales offices for the electrical characteristics in the y version (topr = ?20 c to 105 c).
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 33 of 57 rej03b0183-0210 notes: 1. v cc = 2.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.2 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ??? 240 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ??? 120 ma i oh(peak) peak output ?h? current except p2_0 to p2_7 ??? 10 ma p2_0 to p2_7 ??? 40 ma i oh(avg) average output ?h? current except p2_0 to p2_7 ??? 5ma p2_0 to p2_7 ??? 20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ?? 240 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ?? 120 ma i ol(peak) peak output ?l? current except p2_0 to p2_7 ?? 10 ma p2_0 to p2_7 ?? 40 ma i ol(avg) average output ?l? current except p2_0 to p2_7 ?? 5ma p2_0 to p2_7 ?? 20 ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz f (xcin) xcin clock input oscillation frequency 2.2 v v cc 5.5 v 0 ? 70 khz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected 3.0 v v cc 5.5 v ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.7 v v cc 5.5 v ?? 10 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.2 v v cc 5.5 v ?? 5mhz
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 34 of 57 rej03b0183-0210 figure 5.1 ports p0 to p9 timing measurement circuit notes: 1. v cc /av cc = vref = 2.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. notes: 1. v cc /av cc = vref = 2.7 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this applies when one d/a converter is used and the value of t he dai register (i = 0 or 1) for the unused d/a converter is 00 h. the resistor ladder of the a/d converter is not included. also, even if the vcut bit in the adcon1 register is set to 0 (v ref not connected), i vref flows into the d/a converters. table 5.3 a/d converter characteristics (1) symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bit ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb 10-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 5 lsb 8-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.2 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold v ref = av cc = 2.7 to 5.5 v 0.25 ? 10 mhz with sample and hold v ref = av cc = 2.7 to 5.5 v 1 ? 10 mhz without sample and hold v ref = av cc = 2.2 to 5.5 v 0.25 ? 5mhz with sample and hold v ref = av cc = 2.2 to 5.5 v 1 ? 5mhz table 5.4 d/a converter characteristics (1) symbol parameter conditions standard unit min. typ. max. ? resolution ?? 8bit ? absolute accuracy ?? 1.0 % t su setup time ?? 3 s r o output resistor 4 10 20 k ? i vref reference power input current (note 2) ?? 1.5 ma p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 30pf
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 35 of 57 rej03b0183-0210 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.5 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/2c group 100 (3) ?? times r8c/2d group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 36 of 57 rej03b0183-0210 notes: 1. v cc = 2.7 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 8. ? 40 c for d version. 9. the data hold time includes time that the po wer supply is off or the clock is not supplied. table 5.6 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature ? 20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 37 of 57 rej03b0183-0210 figure 5.2 time delay until suspend notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. table 5.7 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 5.8 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 5.9 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 38 of 57 rej03b0183-0210 notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if ? 20 c t opr 85 c, maintain t w(por1) for 3,000 s or more if ? 40 c t opr < ? 20 c. figure 5.3 power-on reset circuit electrical characteristics table 5.10 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit of hardware manual for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit of hardware manual for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2v external power v cc t rth t rth
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 39 of 57 rej03b0183-0210 notes: 1. v cc = 2.2 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. these standard values show when the fra1 register value after reset is assumed. 3. these standard values show when the correction value in the fra6 register is written to the fra1 register. note: 1. v cc = 2.2 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.11 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature ? supply voltage dependence v cc = 2.7 v to 5.5 v ? 20 c t opr 85 c (2) 39.2 40 40.8 mhz v cc = 2.7 v to 5.5 v ? 40 c t opr 85 c (2) 39.0 40 41.0 mhz v cc = 2.2 v to 5.5 v ? 20 c t opr 85 c (3) 35.2 40 44.8 mhz v cc = 2.2 v to 5.5 v ? 40 c t opr 85 c (3) 34.0 40 46.0 mhz high-speed on-chip oscillator frequency when correction value in fra7 register is written to fra1 register v cc = 5.0 v, t opr = 25 c ? 36.864 ? mhz v cc = 2.7 v to 5.5 v ? 20 c t opr 85 c ? 3% ? 3% % ? value in fra1 register after reset 08h ? f7h ? ? oscillation fr equency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to ? 1 ? +0.3 ? mhz ? oscillation st ability time v cc = 5.0 v, t opr = 25 c ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 550 ? a table 5.12 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation st ability time v cc = 5.0 v, t opr = 25 c ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 5.13 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 40 of 57 rej03b0183-0210 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.14 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 41 of 57 rej03b0183-0210 figure 5.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 42 of 57 rej03b0183-0210 figure 5.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 43 of 57 rej03b0183-0210 figure 5.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 44 of 57 rej03b0183-0210 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.15 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 45 of 57 rej03b0183-0210 note: 1. v cc = 4.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 20 mh z, unless otherwise specified. table 5.16 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = ? 5 ma v cc ? 2.0 ? v cc v i oh = ? 200 av cc ? 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = ? 20 ma v cc ? 2.0 ? v cc v drive capacity low i oh = ? 5 ma v cc ? 2.0 ? v cc v xout drive capacity high i oh = ? 1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = ? 500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v p2_0 to p2_7 drive capacity high i ol = 20 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, trfi, rxd0, rxd1, clk0, clk1, clk2, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v ?? 5.0 a i il input ?l? current vi = 0 v ??? 5.0 a r pullup pull-up resistance vi = 0 v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 46 of 57 rej03b0183-0210 table 5.17 electrical characteristics (2) [vcc = 5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 12 20 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 16 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 7 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5.5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4.5 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 3 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 612ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 150 400 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 150 400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 35 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 30 90 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 18 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.5 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.3 ? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.7 ? a
r8c/2c group, r8c/2d group 5 . electrical characteristics rev.2.10 dec 05, 2007 page 47 of 57 rej03b0183-0210 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at topr = 25 c) [v cc = 5 v] figure 5.8 xin input and xcin input timing diagram when v cc = 5 v figure 5.9 traio input and int1 input timing diagram when v cc = 5 v notes: 1. when using timer rf input capture mode, adjust the cycle ti me to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.10 trfi input timing diagram when v cc = 5 v table 5.18 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.19 traio input, int1 input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns table 5.20 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 400 (1) ? ns t wh(trfi) trfi input ?h? width 200 (2) ? ns t wl(trfi) trfi input ?l? width 200 (2) ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio) t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 5 v
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 48 of 57 rej03b0183-0210 i = 0 to 2 figure 5.11 serial interfa ce timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.12 external interrupt inti input timing diagram when v cc = 5 v table 5.21 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.22 external interrupt inti (i = 0, 2, 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 250 (1) ? ns t w(inl) int0 input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 to 2 v cc = 5 v inti input t w(inl) t w(inh) i = 0, 2, 3 v cc = 5 v
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 49 of 57 rej03b0183-0210 note: 1. v cc =2.7 to 3.3 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 10 mh z, unless otherwise specified. table 5.23 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = ? 1 ma v cc ? 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout drive capacity high i oh = ? 0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 1 ma ?? 0.5 v p2_0 to p2_7 drive capacity high i ol = 5 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, trfi, rxd0, rxd1, clk0, clk1, clk2, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 50 of 57 rej03b0183-0210 table 5.24 electrical characteristics (4) [vcc = 3 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.5 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 11 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.2 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 145 400 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 145 400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 28 85 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 17 50 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.3 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.1 ? a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.65 3.0 a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.65 ? a
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 51 of 57 rej03b0183-0210 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at topr = 25 c) [v cc = 3 v] figure 5.13 xin input and xcin input timing diagram when v cc = 3 v figure 5.14 traio input and int1 input timing diagram when v cc = 3 v notes: 1. when using timer rf input capture mode, adjust the cycle ti me to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.15 trfi input timing diagram when v cc = 3 v table 5.25 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.26 traio input, int1 input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns table 5.27 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 1200 (1) ? ns t wh(trfi) trfi input ?h? width 600 (2) ? ns t wl(trfi) trfi input ?l? width 600 (2) ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) trfi input t wh(trfi) t c(trfi) t wl(trfi) v cc = 3 v
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 52 of 57 rej03b0183-0210 i = 0 to 2 figure 5.16 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.17 external interrupt inti input timing diagram when v cc = 3 v table 5.28 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.29 external interrupt inti (i = 0, 2, 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 380 (1) ? ns t w(inl) int0 input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 to 2 inti input t w(inl) t w(inh) v cc = 3 v i = 0, 2, 3
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 53 of 57 rej03b0183-0210 note: 1. v cc = 2.2 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 5 mhz, unless otherwise specified. table 5.30 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = ? 1 ma v cc ? 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout drive capacity high i oh = ? 0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 1 ma ?? 0.5 v p2_0 to p2_7 drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, trfi, rxd0, rxd1, clk0, clk1, clk2, ssi, scl, sda, sso 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxin feedback resistance xin ? 5 ? m ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 54 of 57 rej03b0183-0210 table 5.31 electrical characteristics (6) [vcc = 2.2 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 2.5 ? ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz no division ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.7 ? ma low-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 110 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 125 350 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 27 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 20 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 12 40 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.8 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 1.9 ? a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.6 3.0 a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.60 ? a
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 55 of 57 rej03b0183-0210 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at topr = 25 c) [v cc = 2.2 v] figure 5.18 xin input and xcin input timing diagram when v cc = 2.2 v figure 5.19 traio input and int1 input timing diagram when v cc = 2.2 v notes: 1. when using timer rf input capture mode, adjust the cycle ti me to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.20 trfi input timing diagram when v cc = 2.2 v table 5.32 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input ?h? width 90 ? ns t wl(xin) xin input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.33 traio input, int1 input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns table 5.34 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 2000 (1) ? ns t wh(trfi) trfi input ?h? width 1000 (2) ? ns t wl(trfi) trfi input ?l? width 1000 (2) ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v trfi input t wh(trfi) t c(trfi) t wl(trfi) v cc = 2.2 v
r8c/2c group, r8c/2d group 5. electrical characteristics rev.2.10 dec 05, 2007 page 56 of 57 rej03b0183-0210 i = 0 to 2 figure 5.21 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.22 external interrupt inti input timing diagram when v cc = 2.2 v table 5.35 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.36 external interrupt inti (i = 0, 2, 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 1000 (1) ? ns t w(inl) int0 input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 to 2 inti input t w(inl) t w(inh) v cc = 2.2 v i = 0, 2, 3
rev.2.10 dec 05, 2007 page 57 of 57 rej03b0183-0210 r8c/2c group, r8c/2d group package dimensions package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. detail f c a l 1 l a 1 a 2 index mark y * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 12.1 12.0 11.9 d 12.1 12.0 11.9 e 1.4 a 2 14.2 14.0 13.8 14.2 14.0 13.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1
a - 1 revision history r8c/2c group, r8c/2d group datasheet rev. date description page summary 0.01 apr 03, 2006 ? first edition issued 0.10 jun 26, 2006 all pages pin name revised cmp0_0 trfo00, cmp0_1 trfo01, cmp0_2 trfo02, cmp1_0 trfo10, cmp1_1 trfo11, cmp1_2 trfo12, trfin trfi 2, 4 table 1.1 specifications for r8c/2c group (1) and table 1.3 specifications for r8c/2d group (1); i/o ports: ? input-only: 3 pins 2 pins revised interrupts: ? internal: 17 sources 23 sources revised 3, 5 table 1.2 specifications for r8c/2c group (2) and table 1.4 specifications for r8c/2d group (2); rom correction function deleted 8 figure 1.3 block diagram revised 9 figure 1.4 pin assignment (top view) revised 10, 11 table 1.7 pin name information by pin number (1) and table 1.8 pin name information by pin number (2) revised 12, 13 table 1.9 pin functions (1) and table 1.10 pin functions (2) revised 19 table 4.1 sfr information (1); ? 0008h: module standby control register, mstcr, 00h added ? 001ch: ?00h? ?00h, 10000000b? revised ? note6 added 20 table 4.2 sfr information (2); ? 005fh: capture interrupt contro l register, capic, xxxxx000b added 22 table 4.4 sfr information (4); ? 00dch: ?00ddh? ?00dch? revised ? 00f5h: ?xxxx00xxb? ?00h? revised 23 table 4.5 sfr information (5); ? 0105h: lin special function register, lincr2, 00h added 31 package dimensions; ?diagrams showing the latest package dimensions ... in the ?packages? section of the renesas technology website.? added 0.20 sep 15, 2006 31 to 54 5. el ectrical characteristics added 0.30 dec 22, 2006 6 table 1.5 and figure 1.1 revised 7 table 1.6 and figure 1.2 revised 17 figure 3.1 revised 18 figure 3.2 revised 19 table 4.1; ? 000ah: ?00xxx000b? ?00h? revised ? 0008h: ?module standby control register? ?module operation enable register? revised ? 000fh: ?00011111b? ?00x11111b? revised 37 table 5.11 revised r8c/2c group, r8c/2d group datasheet revision history
a - 2 revision history r8c/2c group, r8c/2d group datasheet 1.00 feb 09, 2007 all pages ?preliminary? deleted 3 table 1.2 revised 5 table 1.4 revised 6 table 1.5 and figure 1.1 revised 7 table 1.6 and figure 1.2 revised 17 figure 3.1 revised 18 figure 3.2 revised 19 table 4.1; ? 0008h: ?module standby control register? ?module operation enable register? revised ? 000ah: ?00xxx000b? ?00h? revised ? 000fh: ?00011111b? ?00x11111b? revised ? 002bh: ?high-speed on-chip osc illator control re gister 6? added 23 table 4.5; 0105h: ?lin control register 2? register name revised 31 table 5.2 revised 32 table 5.3 and table 5.4; note1 revised 37 table 5.11 revised 44 table 5.17 revised 46 table 5.21 and figure 5.11; ?i = 0 to 2? revised 48 table 5.24 revised 50 table 5.28 revised, figure 5.16; ?i = 0 to 2? revised 52 table 5.31 revised 53 table 5.34 revised 54 table 5.35 and figure 5.21; ?i = 0 to 2? revised 2.00 oct 17, 2007 all pages y version added 6, 7 table 1.5, table 1.6 (d) mark is deleted 31 table 5.1 rated value: ?tbd? ?700? 2.10 dec 05, 2007 2, 4 table 1.1, table 1.3 cl ock: ?real-time clock (timer re)? added 6, 7 table 1.5 and figure 1.1 revised 8 table 1.6 and figure 1.2 revised 18, 19 figure 3.1 and figure 3.2 revised 20 table 4.1 002ch: high-s peed on-chip oscillato r control register 7 added 23 table 4.4 00f5h: after reset ?00h? ?000000xxb? revised 33 table 5.2 note2 revised 39 table 5.11 revised rev. date description page summary all trademarks and registered trademarks are the property of their respective owners.
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